The present invention is generally directed to field programmable gate array (FPGA) circuits, a more specifically to an FPGA circuit in which logic functions may be implemented by the interconnect circuitry between logic blocks.
The speed, power, and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, have increased dramatically in the last twenty years. More recently, these increases have led to development of so-called system-on-a-chip (SoC) devices. A SoC device allows nearly all of the components of a complex system, such as a cell phone or a television receiver, to be integrated onto a single piece of silicon. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
A key component in many highly integrated circuits, including SoC devices, is the field programmable gate array (FPGA). FPGA circuits are a particular class of general purpose integrated circuits (ICs) that can be configured (i.e., programmed) to perform a wide range of tasks. There are a number of different types of FPGA circuit topologies, including symmetrical array, row-based, sea-of-gates, and hierarchical programmable logic device (PLD). Each of these FPGA types has certain advantages over other types, depending on the specific application.
FPGA circuits generally are implemented using one of four technologies: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. In static RAM technology, programmable connections in the FPGA are made using pass transistors, transmission gates, or multiplexers controlled by a static random access memory (RAM) cell. Static RAM cells technology allow fast reconfiguration of a FPGA circuit. Anti-fuse technology uses an anti-fuse that is initially a high-impedance connection path (i.e., open circuit). The anti-fuse is then programmed into a low impedance (i.e., short circuit) or fused state. While anti-fuse technology is simple and less expensive than static RAM technology, an anti-fuse is a xe2x80x9cprogram oncexe2x80x9d device. EPROM and EEPROM technologies use the same methods that are used in EPROM memories.
There are three primary configurable elements in a FPGA circuit: configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs) programmable logic devices (PLDs), and the like. A programmable interconnect generally connects a single output of a CLB to an input of another CLB. An interconnect comprises metal wires and transistors that act as pass gates and signal buffers that preserve the signal integrity. Control of the interconnect transistors may be provided by an SRAM cell, a flash RAM cell, or external pins. The programming of an interconnect is usually done in a static fashion, such as at the power-up of a stand-alone FPGA circuit, especially for flash RAM and SRAM based configurations. The I/O blocks provide the interface between the external pins of the IC package and the internal signals lines, including the programmable interconnects.
Despite the considerable advancements made in field programmable gate array circuits, however, there remains room for improvement. There is a limitation to the complexity of the logic functions that may be implemented in a FPGA circuit of a particular size and density. More complex functions call for still greater FPGA density. However, this greater density must be achieved without incurring larger latencies due to increased propagation times through the FPGA circuit.
Therefore, there is a need in the art for system-on-a-chip (SoC) devices and other large scale integrated circuits that implement improved field programmable gate array (FPGA) circuits. In particular, there is a need for FPGA circuits, including embedded FPGA circuits, that achieve greater density and/or utilization over standard FPGA technologies. More particularly, there is a need for improved FPGA circuits that are capable of performing more complex logical functions while minimizing propagation times.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a field programmable gate array capable of performing selected functions, such as bit swapping, in the interconnect matrix that are normally performed in the configurable logic blocks of the FPGA. According to an advantageous embodiment of the present invention, the field programmable gate array comprises: 1) a plurality of configurable logic blocks, including a first configurable logic block (CLB) having an N-bit output and a second configurable logic block (CLB) having an N-bit input; 2) a plurality of interconnects; 3) a plurality of interconnect switches capable of coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller capable of controlling the plurality of interconnect switches, wherein the interconnect switch controller in a first switch configuration causes a first group of interconnects coupled to the N-bit output of the first CLB to be coupled to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping and wherein the interconnect switch controller in a second switch configuration causes the first group of interconnects to be coupled to the second group of interconnects according to a second connection mapping.
According to one embodiment of the present invention, the interconnect switch controller comprises a memory capable of storing the first and second switch configurations.
According to another embodiment of the present invention, the memory comprises a static read only memory.
According to still another embodiment of the present invention, the interconnect switch controller comprises at least one configurable logic block in the field programmable gate array.
According to yet another embodiment of the present invention, the first connection mapping causes the N-bit output of the first CLB having a first endian format to be coupled to the N-bit input of the second CLB in the first endian format and wherein the second connection mapping causes the N-bit output of the first CLB having the first endian format to be coupled to the N-bit input of the second CLB in a second endian format.
According to a further embodiment of the present invention, the first connection mapping causes a least significant bit of the N-bit output of the first CLB to be coupled to a least significant bit of the N-bit input of the second CLB and causes the remaining Nxe2x88x921 bits of the N-bit output in an increasing order of significance to be coupled to the remaining Nxe2x88x921 bits of the N-bit input in an increasing order of significance.
According to a still further embodiment of the present invention, the second connection mapping causes a least significant bit of the N-bit output of the first CLB to be coupled to a most significant bit of the N-bit input of the second CLB and causes the remaining Nxe2x88x921 bits of the N-bit output in an increasing order of significance to be coupled to the remaining Nxe2x88x921 bits of the N-bit input in a decreasing order of significance.
According to a yet further embodiment of the present invention, the first connection mapping causes the bits in a least significant byte of the N-bit output of the first CLB to be coupled to corresponding ones of the bits in a least significant byte of the N-bit input of the second CLB and causes the bits in a most significant byte of the N-bit output of the first CLB to be coupled to corresponding ones of the bits in a most significant byte of the N-bit input of the second CLB.
In one embodiment of the present invention, the second connection mapping causes the bits in the least significant byte of the N-bit output of the first CLB to be coupled to corresponding ones of the bits in the most significant byte of the N-bit input of the second CLB and causes the bits in the most significant byte of the N-bit output of the first CLB to be coupled to corresponding ones of the bits in the least significant byte of the N-bit input of the second CLB.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.